1. Field of the Invention
The invention relates to a circuit arrangement for controlling the access to a memory by at least two processors, in which a clock-pulse controlled control circuit that receives request signals from the processors, generates control signals therefrom for access to the memory, and interrupts the execution of an access for a processor when a request signal from the privileged processor appears before termination of said access.
2. Description of the Related Art
A circuit arrangement of this kind is known from DE-OS 35 02 721. Therein, an address register is provided for each processor, but the data terminal of the memory is connected to the corresponding data terminals of the processors, without intermediate buffering, via controlled bus switches. However, many processors require a significant period of time, for example several clock pulse cycles of a clock signal, for delivering and notably for accepting data, and during this time the memory must remain addressed in order to ensure that the data remains valid until the instant of processing or acceptance. Furthermore, when the access by a processor of lower priority is interrupted by the privileged processor, the processor of lower priority must continuously repeat its request until access to the memory has become free. This requires not only a substantial amount of time, but also additional steps as regards the software. The maximum speed of successive accesses, therefore, is not determined by the speed of the memory but by the corresponding speed of the accessing processors.
Memories (Dual Port Memories) for the access of two ports, in particular of two processors, which use data registers are already known. For example, memory arrangements in which the data to be recorded in the memory are temporarily recorded in registers, are described in Japanese Patent Application 63-183678 (English abstract) as well as in IEEE ISSCC Konferenzberichte, February 1985, pp. 44 and 45. Furthermore, a memory control is described in U.S. Pat. No. 4,796,232 in which a data register is provided only for the one processor for the data read from the memory. This patent publication does not describe data registers for both data to be recorded and read data, and the processors or other elements having access to the memory all mutually rank equally and each started access is terminated completely before an access from another port is started.